Analog-to-digital converters are widely used to generate, from an analog input signal, a corresponding digital signal. The digital signal is actually a stream of (generally multi-bit) digitized values, each representing one sample of the analog input signal. These digital values may be used, for example, in digital signal processing algorithms to extract information from or transform the input signal in some way. Numerous types of converters exist for transforming analog signal samples to digital form. Each different type of converter has its particular advantages and disadvantages, and represents a trade-off among a number of operational and manufacturing characteristics.
Among the known types of analog-to-digital converters are so-called "flash", or parallel, converters. FIG. 1 illustrates a typical block diagram for a basic flash converter 10. The converter employs 2.sup.N -1 latched analog comparators 12.sub.0 . . . 12.sub.M (where M=2.sup.n -2) in parallel, where N is the number of bits of resolution in the desired digital output. A resistive voltage divider 14 driven by a stable reference source 16 provides the reference voltages for the comparators. The reference voltage for each comparator is at least one least-significant-bit (LSB) higher than the reference voltage for the comparator immediately below it.
When an analog input signal is present at the input of the comparator bank, all comparators which have a reference voltage below the level of the input signal will assume a logic "1" output. The comparators which have their reference voltage above the input signal will have a logic "0" output. This is referred to as a "thermometer" code.
Thus, except during transitions, the output of each comparator is either a high level, representing a binary 1, or a low level, representing a binary 0. However, since a finite time is required for the comparator outputs to change states when they are strobed and latched, the comparator output signals are not reliable until they have settled to their final values. Furthermore, if the input signal changes while the comparators are settling, the outputs can be erratic due to variations in dynamic performance among the comparators. Therefore, high-speed, high-resolution systems often employ an external track-and-hold circuit (not shown) which holds the analog input constant while the comparators are settling.
A decoding (or encoding, the two terms being synonomous herein) stage 18 receives the outputs of the comparators and converts them (directly or eventually) into a binary digital output. The decoding stage may assume several forms. For example, the decoding stage may be implemented as combinational logic. However, this approach requires a lot of semiconductor area and a considerable amount of power consumption. Therefore, another approach (illustrated in FIG. 1) is generally used, with the decoding stage implemented as a "one-of" circuit (OOC) 20 followed by one or two read-only memories (ROM's) 22. In the two-ROM systems such as the one shown in FIG. 1, a first ROM 22-1 generates a Gray-code or modified Gray-code digital output word from the OOC output and a second ROM 22-2 or a logic decode circuit converts the output of the first ROM to a binary-value word. In the single ROM systems, not shown, one ROM serves as a look-up table which directly provides a binary output from the OOC output. The difference between the one- and two-ROM approaches is discussed further below. Either way, the output of ROM(s) 22 typically is supplied to the rest of the system via a buffer (not shown).
Additional general background information on flash converters is contained in Analog-Digital Conversion Handbook (3d ed.; Daniel H. Sheingold, editor), Prentiss-Hall, Englewood Cliffs, N.J., 1986, pages 420-427, incorporated by reference.
In practice, due to mismatches and imperfections in the reference resistor ladder and in the latched comparators, as well as dynamic considerations such as those mentioned above, it does not always happen that a perfect thermometer code is produced at the comparator outputs. Sometimes, a comparator output which should be a "1" actually appears as a "0" at the instant the outputs of the comparators are read. This may happen, for example, if a comparator switches more slowly than is expected, so that the output is latched before it has reached its final state. When a "0" is sandwiched between two "1's" in the (one-dimensional) array of comparator outputs, an ambiguity may exist as to the value of the input signal. For example, if it is assumed that only a one-bit error occurred, either the sandwiched "0" may be an error or one of the two adjacent "1's" may be an error. Since such an error is analogous to a bubble occurring in the liquid of a mercury or alcohol thermometer, errors in the thermometer code often are called "bubbles" in the code. Of course, in addition to one-bit errors, two-bit (and higher order) errors (both adjacent and separated) also occur, though with lesser frequency. Consequently, numerous possible error conditions can exist and lead to erroneous interpretations of the output array from the comparators.
To appreciate the impact of bubbles in the thermometer code, it is helpful to understand how the thermometer code is decoded to provide an N-bit digital output word. As stated above, generally, two approaches exist. The first approach is to use a large amount of combinational logic to decode the possible arrangements of the comparator outputs. The design of such logic is explained in the literature. Error correction is built right into the logic, to the extent there is a defined output for a defined input. To reduce the necessary amount of circuitry and corresponding power consumption, the circuitry may not decode every conceivable input, since some of the potential inputs involve unlikely multiple-bit errors.
In the second approach, a "one-of" circuit ("OOC") reads the comparator outputs and detects the location of any 1-to-0 transitions in the thermometer code. (By convention, the transition under consideration is generally from a "lower" comparator output to a "higher" comparator output, where lower and higher refers to placement along the resistive ladder. The OOC has one output line for each possible value of the input signal--i.e., 2.sup.N -1 output lines. All output lines are held at a value of 0 except the output line which is mapped to the location of the detected transition. The output whose value is 1 is supposed to correspond to the most significant comparator output whose value is 1--i.e., the transition point in the thermometer code. In an ideal situation, this identifies the value of the input signal. However, if there is a bubble in the thermometer code, there will be multiple 0-to-1 transitions in the thermometer code, so there will be more than one "1" in the OOC output. This condition is referred to as "sparkle" or "sparkle codes" in the output of the OOC: one or more erroneous 0-to-1 transitions.
Each OOC output addresses (i.e., enables) a single (word length) location in a ROM. There is one N-bit ROM location for each of the 2.sup.N -1 output lines of the OOC. When an OOC output line carries a voltage corresponding to a logical 1 value, the corresponding ROM location is said to be "enabled" and its contents are impressed on the ROM output bit lines and provided as the ROM output. The ROM thus serves as a look-up table to decode the meaning of the OOC outputs.
If a single-step ROM conversion process is used, the codes stored in the ROM locations are binary values corresponding to the OOC output lines. Sparkle codes, however, can cause large errors in the decoding of the OOC output. By virtue of ROM construction, if two or more ROM locations are enabled by multiple 1's in the OOC output, the ROM output will be the logical AND or OR of the contents of those locations. This can produce a digital output value which may contain large errors, since the logical combination of two binary values could be very different from either of them.
To reduce the magnitude of such errors, the OOC output is sometimes converted in a first ROM (22-1) to a Gray- or modified Gray-code, which is then converted to a binary code in a second ROM (22-2). This is helpful because the logical combination of two Gray- (or similarly) coded numbers generally is closer in value to at least one of them than is true for a similar combination of pure binary numbers.
Overall, many performance characteristics of the converter are influenced considerably by the design of the ROM or ROMs in the decoding stage. The selection of a particular circuit architecture for the ROM(s) will impact power consumption, conversion speed, and other specifications. The present invention has utility with respect to ROM's fabricated in metal-oxide semiconductor (MOS) technology.
Referring to FIG. 2, a portion is illustrated of one type of an exemplary MOS ROM 25. Just two ROM locations 24 and 26 are depicted, each for storing four bits of information to be supplied (eventually, when the location is read) via ROM data lines (i.e., bit lines) B1-B4. In each location, one transistor is provided for each zero-valued bit of information to be stored in the ROM; current sources 28.sub.1 -28.sub.4 charge the bit lines high and those transistors pull the corresponding bit lines low. Information is stored in (i.e., impressed upon) a ROM location by providing and permanently connecting, for each zero-valued bit, one NMOS transistor with its drain connected to the bit line and its source connected to ground. All other bits automatically will be set to a logical high, or 1, value by the presence of the current sources. It will be appreciated, of course, that the design is extendable to a ROM of arbitrary size (as are all the ROM designs discussed herein). For purposes of this description, each collection of transistors corresponding to a given ROM address is referred to as a ROM "location." As shown in FIG. 2, each location has at most one transistor connected to control the state of each of the corresponding output bit lines B1 . . . Bn (where in this case, n=4). Each bit line is also connected to a supply voltage V+ via a current source 28.sub.i (where i is just a subscript placeholder). The transistors for a location are selectively turned on by the OOC output lines. That is, all of the transistors for a given ROM location have their gates connected together and to one output of the OOC. If the OOC output is high, or logical 1 value, the transistors are turned on; if the OOC output is low, the transistors are turned off. The bit lines not having such transistors are always high.
The current sources are sized to pull the bit lines toward V+, by charging the parasitic capacitance on the input of the next stage (often a buffer) driven by the bit lines, and ensuring a 1 output when all pull-down transistors on the bit line are turned off.
With a suitable change in the topology (i.e., connecting the current sources between the bit lines and ground), PMOS transistors can be used instead of NMOS transistors, of course.
The use of a design such as that of FIG. 2 imposes a tradeoff between speed and power (current) consumption. To charge the parasitic capacitance faster, a larger current source is needed. However, to discharge the parasitic capacitance and pull down the bit line against a larger current source, the transistor must be larger and it must carry more current. This both increases the chip area which must be devoted to the transistor and increases the current drawn by the ROM during static and switching conditions. Yet the designer generally will want to reduce the current required by the ROM (both statically and dynamically) and use minimum chip area, while also providing a high speed memory. Consequently, these criteria are in conflict and tradeoffs are required.
To reduce the static current drain which arises from the use of current sources which are always on, a ROM implementation such as that of FIG. 3 (at 30) is sometimes employed. (Only two ROM locations are shown.) In this approach, a transistor is provided only for ROM cells which are to be set to zero. The source of each such ROM cell transistor 32i,34i is grounded and its drain is connected to a high-impedance bit line (B1 . . . Bn). Each bit line B.sub.j is also connected to the drain of a precharge transistor 36.sub.j. The sources of the precharge transistors are connected to a voltage source V.sub.DD and all of the precharge transistors have their gates connected together to receive a precharge pulse (applied at 38). When the precharge pulse turns on the precharge transistors, the bit lines are charged to a high, logical 1 level. They remain in that state unless pulled low by one of the ROM cell transistors. This configuration meets the goal of reduced static current requirements, but it requires the addition of control circuitry (not shown) for precharging the bit lines in advance of each conversion cycle and it increases susceptibility to noise (i.e., the potential for electrical noise to corrupt the output data). When the precharge transistors are turned off, the high impedance bit lines are at times not being driven. They can therefore pick up noise easily. Additionally, switching transients can be coupled between such high impedance lines in very unpredictable ways; for example, a bit line may go low due to a high speed switching node capacitively coupling noise into the ROM data line.
As stated above, the principal technique for minimizing the errors cause by sparkle code in the OOC output is to employ a "one-of" to Gray- (or modified-Gray-) code converter ROM cascaded with a Gray- (or modified-Gray-) code to binary-code converter ROM. However, this does not, in and of itself, eliminate the problem of high impedance bit lines.